ELECTRONIC TOLL COLLECTION SYSTEM
A specific MCU design of On board Unit (OBU) in Electronic Toll Collection (ETC) system is proposed in this paper. According to the ETC applications, this MCU is designed to have the minimum application system. Results show that this MCU design scheme is feasible and fulfills the requirements of the central control chip used for OBU in ETC system. The MCU has about 113,000 gates, and its area is 642.74 !-lm x 494.20 !-lm under SMIC 65nm technology. The average power consumption is 98!-lW. Compared with the general MCU, the MCU has a larger advantage in ETC application.
IMPLEMENTATION & RESULTS
Function Simulation The design verification includes memory operation and interface protocol. This design uses Verilog HDL to write RTL code and build a test platform. Verification platform contains memory model, SPI master model, SPI slave model, and UART model. The function verification is based on Cadence simulation tool NC-Verilog. The method of Hardware Software Co-design is used to verify the function of each module. All kinds of operation are performed using bootloader, driver and application program. Program is loaded into memory model by $readmemh or $readmemb command. Figure 4 is the function simulation results of memories and peripheral interfaces. The timing of these modules meets the requirements of the specification, and signals are correct compared with the expectation.
The design verification plan is divided into the following stages: First, the UART interface is tested. The program download interface which is cured in ROM is used to test UART interface in this design. Since the UART interface can be used to observe the intuitive behavior and internal data, so it is used to test other modules. Then, EFLASH is tested. Chip download function is tested by constantly writing data to the EFLASH program area through UART interface and verifying the correctness while downloading. After this test, EFLASH can download program used to Hardware Software Co-verification. This facilitates the subsequent verification. Finally, the SPI interface is tested. The SPI interface is tested through communicating with 13.56M reader chip and 5.8G RF chip which are high reliability chips. After that, the GPIO and other function modules are also tested. The results of FPGA verification show that the design meets the function requirements of OBU in ETC system.
CONCLUSION This paper completes the specific MCU of OBU in ETC. The chip successfully integrates ARM IP core, ROM, SRAM, EFLASH, MMU, SPI master, SPI slave, UART, GPIO, and interrupt interfaces. By successfully implementing the minimum application system and using clock gating technique, the characteristics of central control chip of OBU in ETC are realized. Results show that the MCU only has about 113,000 gates, occupies 642.74fill1 x 494.20 fill1 area, and consumes on average 98!! W power under SMIC 65nm technology. Compared with the general MCU, this MCU has a significant advantage and lays a good foundation for further development of the theory and Practice for OBU in ETC.